IndiumV3, Russie, Analysis, bibRecord, 000698

4x288 linear FPA on the Heteroepitaxial Hg1-xCdxTe Base

Identifieur interne : 000698 ( Russie/Analysis ); précédent : 000697; suivant : 000699

4x288 linear FPA on the Heteroepitaxial Hg1-xCdxTe Base

Auteurs : RBID : Pascal:04-0285151

Descripteurs français

Pascal (Inist)
- Matrice plan focal, Barrette linéaire, Rayonnement IR lointain, Diode, Dispositif CCD, Essai, Epitaxie jet moléculaire, Fréquence coupure, Recombinaison porteur charge, Processus recombinaison, Multiplexeur, Circuit entrée, Conception circuit, Circuit intégré, Pastille électronique, Partitionnement, Canal n, Technologie MOS, Canal enterré, Horloge, Jonction p n, Couche tampon.
Wicri :
- concept : Essai.

English descriptors

KwdEn :
- Buffer layer, Buried channel, Charge carrier recombination, Charge coupled device, Circuit design, Clock, Cut off frequency, Diode, Far infrared radiation, Focal plane arrays, Input circuit, Integrated circuit, Linear array, MOS technology, Molecular beam epitaxy, Multiplexer, Partitioning, Recombination process, Test, Wafer, n channel, p n junction.

Abstract

4×288 heteroepitaxial mercury-cadmium telluride (MCT) linear arrays for long wavelength infrared (LWIR) applications with 28×25 micron diodes and charge coupled devices (CCD) silicon readouts were designed, manufactured and tested. MCT heteroepitaxial layers were grown by MBE technology on (013) GaAs substrates with CdZnTe buffer layers and have cutoff wavelength λ_co ≃ 11.8 μm at T = 78 K. To decrease the surface influence of the carriers recombination processes the layers with composition changes and its increase both toward the surface and HgCdTe/CdZnTe boundary were grown. Silicon read-outs with CCD multiplexers with input direct injection circuits were designed, manufactured and tested. The testing procedure to qualify read-out integrated circuits (ROICs) on wafer level at T= 300 K was worked out The silicon read-outs for 4x288 arrays, with skimming and partitioning functions included were manufactured by n-channel MOS technology with buried or surface channel CCD register. Designed CCD readouts are driven with four- or two-phase clock pulses. The HgCdTe arrays and Si CCD readouts were hybridized by cold welding indium bumps technology. With skimming mode used for 4x288 MCT n-p-junctions, the detectivity was about D*_λ ≅ 9×10¹⁰ cm×Hz^1/2/W for background temperature T_b = 295 K.

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Le document en format XML

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<profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Buffer layer</term>
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<term>Charge carrier recombination</term>
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<term>Circuit design</term>
<term>Clock</term>
<term>Cut off frequency</term>
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<term>Integrated circuit</term>
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<front><div type="abstract" xml:lang="en">4×288 heteroepitaxial mercury-cadmium telluride (MCT) linear arrays for long wavelength infrared (LWIR) applications with 28×25 micron diodes and charge coupled devices (CCD) silicon readouts were designed, manufactured and tested. MCT heteroepitaxial layers were grown by MBE technology on (013) GaAs substrates with CdZnTe buffer layers and have cutoff wavelength λ<sub>co</sub>
 ≃ 11.8 μm at T = 78 K. To decrease the surface influence of the carriers recombination processes the layers with composition changes and its increase both toward the surface and HgCdTe/CdZnTe boundary were grown. Silicon read-outs with CCD multiplexers with input direct injection circuits were designed, manufactured and tested. The testing procedure to qualify read-out integrated circuits (ROICs) on wafer level at T= 300 K was worked out The silicon read-outs for 4x288 arrays, with skimming and partitioning functions included were manufactured by n-channel MOS technology with buried or surface channel CCD register. Designed CCD readouts are driven with four- or two-phase clock pulses. The HgCdTe arrays and Si CCD readouts were hybridized by cold welding indium bumps technology. With skimming mode used for 4x288 MCT n-p-junctions, the detectivity was about D*<sub>λ</sub>
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 ≃ 11.8 μm at T = 78 K. To decrease the surface influence of the carriers recombination processes the layers with composition changes and its increase both toward the surface and HgCdTe/CdZnTe boundary were grown. Silicon read-outs with CCD multiplexers with input direct injection circuits were designed, manufactured and tested. The testing procedure to qualify read-out integrated circuits (ROICs) on wafer level at T= 300 K was worked out The silicon read-outs for 4x288 arrays, with skimming and partitioning functions included were manufactured by n-channel MOS technology with buried or surface channel CCD register. Designed CCD readouts are driven with four- or two-phase clock pulses. The HgCdTe arrays and Si CCD readouts were hybridized by cold welding indium bumps technology. With skimming mode used for 4x288 MCT n-p-junctions, the detectivity was about D*<sub>λ</sub>
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<s5>02</s5>
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<fC03 i1="02" i2="X" l="SPA"><s0>Barreta lineal</s0>
<s5>02</s5>
</fC03>
<fC03 i1="03" i2="X" l="FRE"><s0>Rayonnement IR lointain</s0>
<s5>03</s5>
</fC03>
<fC03 i1="03" i2="X" l="ENG"><s0>Far infrared radiation</s0>
<s5>03</s5>
</fC03>
<fC03 i1="03" i2="X" l="SPA"><s0>Radiación infrarroja lejana</s0>
<s5>03</s5>
</fC03>
<fC03 i1="04" i2="X" l="FRE"><s0>Diode</s0>
<s5>04</s5>
</fC03>
<fC03 i1="04" i2="X" l="ENG"><s0>Diode</s0>
<s5>04</s5>
</fC03>
<fC03 i1="04" i2="X" l="SPA"><s0>Diodo</s0>
<s5>04</s5>
</fC03>
<fC03 i1="05" i2="X" l="FRE"><s0>Dispositif CCD</s0>
<s5>05</s5>
</fC03>
<fC03 i1="05" i2="X" l="ENG"><s0>Charge coupled device</s0>
<s5>05</s5>
</fC03>
<fC03 i1="05" i2="X" l="SPA"><s0>Dispositivo carga acoplada</s0>
<s5>05</s5>
</fC03>
<fC03 i1="06" i2="X" l="FRE"><s0>Essai</s0>
<s5>06</s5>
</fC03>
<fC03 i1="06" i2="X" l="ENG"><s0>Test</s0>
<s5>06</s5>
</fC03>
<fC03 i1="06" i2="X" l="SPA"><s0>Ensayo</s0>
<s5>06</s5>
</fC03>
<fC03 i1="07" i2="3" l="FRE"><s0>Epitaxie jet moléculaire</s0>
<s5>07</s5>
</fC03>
<fC03 i1="07" i2="3" l="ENG"><s0>Molecular beam epitaxy</s0>
<s5>07</s5>
</fC03>
<fC03 i1="08" i2="X" l="FRE"><s0>Fréquence coupure</s0>
<s5>08</s5>
</fC03>
<fC03 i1="08" i2="X" l="ENG"><s0>Cut off frequency</s0>
<s5>08</s5>
</fC03>
<fC03 i1="08" i2="X" l="SPA"><s0>Frecuencia corte</s0>
<s5>08</s5>
</fC03>
<fC03 i1="09" i2="X" l="FRE"><s0>Recombinaison porteur charge</s0>
<s5>09</s5>
</fC03>
<fC03 i1="09" i2="X" l="ENG"><s0>Charge carrier recombination</s0>
<s5>09</s5>
</fC03>
<fC03 i1="09" i2="X" l="SPA"><s0>Recombinación portador carga</s0>
<s5>09</s5>
</fC03>
<fC03 i1="10" i2="X" l="FRE"><s0>Processus recombinaison</s0>
<s5>10</s5>
</fC03>
<fC03 i1="10" i2="X" l="ENG"><s0>Recombination process</s0>
<s5>10</s5>
</fC03>
<fC03 i1="10" i2="X" l="SPA"><s0>Proceso recombinación</s0>
<s5>10</s5>
</fC03>
<fC03 i1="11" i2="X" l="FRE"><s0>Multiplexeur</s0>
<s5>11</s5>
</fC03>
<fC03 i1="11" i2="X" l="ENG"><s0>Multiplexer</s0>
<s5>11</s5>
</fC03>
<fC03 i1="11" i2="X" l="SPA"><s0>Multiplexor</s0>
<s5>11</s5>
</fC03>
<fC03 i1="12" i2="X" l="FRE"><s0>Circuit entrée</s0>
<s5>12</s5>
</fC03>
<fC03 i1="12" i2="X" l="ENG"><s0>Input circuit</s0>
<s5>12</s5>
</fC03>
<fC03 i1="12" i2="X" l="SPA"><s0>Circuito entrada</s0>
<s5>12</s5>
</fC03>
<fC03 i1="13" i2="X" l="FRE"><s0>Conception circuit</s0>
<s5>13</s5>
</fC03>
<fC03 i1="13" i2="X" l="ENG"><s0>Circuit design</s0>
<s5>13</s5>
</fC03>
<fC03 i1="13" i2="X" l="SPA"><s0>Diseño circuito</s0>
<s5>13</s5>
</fC03>
<fC03 i1="14" i2="X" l="FRE"><s0>Circuit intégré</s0>
<s5>14</s5>
</fC03>
<fC03 i1="14" i2="X" l="ENG"><s0>Integrated circuit</s0>
<s5>14</s5>
</fC03>
<fC03 i1="14" i2="X" l="SPA"><s0>Circuito integrado</s0>
<s5>14</s5>
</fC03>
<fC03 i1="15" i2="X" l="FRE"><s0>Pastille électronique</s0>
<s5>15</s5>
</fC03>
<fC03 i1="15" i2="X" l="ENG"><s0>Wafer</s0>
<s5>15</s5>
</fC03>
<fC03 i1="15" i2="X" l="SPA"><s0>Pastilla electrónica</s0>
<s5>15</s5>
</fC03>
<fC03 i1="16" i2="X" l="FRE"><s0>Partitionnement</s0>
<s5>16</s5>
</fC03>
<fC03 i1="16" i2="X" l="ENG"><s0>Partitioning</s0>
<s5>16</s5>
</fC03>
<fC03 i1="16" i2="X" l="SPA"><s0>Subdivisión</s0>
<s5>16</s5>
</fC03>
<fC03 i1="17" i2="X" l="FRE"><s0>Canal n</s0>
<s5>17</s5>
</fC03>
<fC03 i1="17" i2="X" l="ENG"><s0>n channel</s0>
<s5>17</s5>
</fC03>
<fC03 i1="17" i2="X" l="SPA"><s0>Canal n</s0>
<s5>17</s5>
</fC03>
<fC03 i1="18" i2="X" l="FRE"><s0>Technologie MOS</s0>
<s5>18</s5>
</fC03>
<fC03 i1="18" i2="X" l="ENG"><s0>MOS technology</s0>
<s5>18</s5>
</fC03>
<fC03 i1="18" i2="X" l="SPA"><s0>Tecnología MOS</s0>
<s5>18</s5>
</fC03>
<fC03 i1="19" i2="X" l="FRE"><s0>Canal enterré</s0>
<s5>19</s5>
</fC03>
<fC03 i1="19" i2="X" l="ENG"><s0>Buried channel</s0>
<s5>19</s5>
</fC03>
<fC03 i1="19" i2="X" l="SPA"><s0>Canal enterrado</s0>
<s5>19</s5>
</fC03>
<fC03 i1="20" i2="X" l="FRE"><s0>Horloge</s0>
<s5>20</s5>
</fC03>
<fC03 i1="20" i2="X" l="ENG"><s0>Clock</s0>
<s5>20</s5>
</fC03>
<fC03 i1="20" i2="X" l="SPA"><s0>Reloj</s0>
<s5>20</s5>
</fC03>
<fC03 i1="21" i2="X" l="FRE"><s0>Jonction p n</s0>
<s5>21</s5>
</fC03>
<fC03 i1="21" i2="X" l="ENG"><s0>p n junction</s0>
<s5>21</s5>
</fC03>
<fC03 i1="21" i2="X" l="SPA"><s0>Unión p n</s0>
<s5>21</s5>
</fC03>
<fC03 i1="22" i2="X" l="FRE"><s0>Couche tampon</s0>
<s5>22</s5>
</fC03>
<fC03 i1="22" i2="X" l="ENG"><s0>Buffer layer</s0>
<s5>22</s5>
</fC03>
<fC03 i1="22" i2="X" l="SPA"><s0>Capa tampón</s0>
<s5>22</s5>
</fC03>
<fN21><s1>173</s1>
</fN21>
<fN44 i1="01"><s1>OTO</s1>
</fN44>
<fN82><s1>OTO</s1>
</fN82>
</pA>
<pR><fA30 i1="01" i2="1" l="ENG"><s1>International conference on photoelectronics and night vision devices</s1>
<s2>17</s2>
<s3>Moscow RUS</s3>
<s4>2002-05-27</s4>
</fA30>
</pR>
</standard>
</inist>
</record>

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   |wiki=   *** parameter Area/wikiCode missing *** 
   |area=    IndiumV3
   |flux=    Russie
   |étape=   Analysis
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   |clé=     Pascal:04-0285151
   |texte=   4x288 linear FPA on the Heteroepitaxial Hg1-xCdxTe Base
}}

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4x288 linear FPA on the Heteroepitaxial Hg1-xCdxTe Base

4x288 linear FPA on the Heteroepitaxial Hg1-xCdxTe Base

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